Distributed decoding of cyclic block codes using a generalization of majority-logic decoding

Low Power Error Correcting Codes Using Majority Logic Decoding

A low-density parity-check (LDPC) code is a linear error correcting code, and is used for transmitting message over a noisy transmission channel. A new class of error correcting codes called EG-LDPC (Euclidean Geometry-LDPC) codes and its encoder and decoder architectures for nanomemory applications is designed. EG-LDPC codes also have fault secure detection capability. One step majority logic ...

Modified majority logic decoding of cyclic codes in hybrid-ARQ systems

Reliability information provided by sets of orthogonal check sums in a majority logic decoder for block codes is used in a type-I hybrid ARQ error control scheme. The reliability information is obtained through a simple modification of the majority logic decoding rule. It is shown that the reliability performance of Reed-Muller and other majority logic decodable codes can be substantially impro...

A New Iterative Threshold Decoding Algorithm for One Step Majority Logic Decodable Block Codes

The performance of iterative decoding algorithm for one-step majority logic decodable (OSMLD) codes is investigated. We introduce a new soft-in soft-out of APP threshold algorithm which is able to decode theses codes nearly as well as belief propagation (BP) algorithm. However the computation time of the proposed algorithm is very low. The developed algorithm can also be applied to product code...

Decoding of Block Turbo Codes

Comdined Turbo Block Decoding and Equalisation

In this paper, the combination of equalization and turbo decoding is studied. In the iterative decoding of a product code in block turbo coding system, the equalization process is performed within the iteration loop. The present study aims to investigate the decision feedback equalizer (DFE) incorporated in the iterative decoding. Simulation results show that the more severe the channel interfe...